pub struct PLL {
pub ba: [Q32<32>; 3],
}Expand description
Type-2, order-3 sampled phase, discrete time PLL
This PLL tracks the frequency and phase of an input signal with respect to the sampling clock. The open loop transfer function is type 2 (DC double integrator) from input phase to output phase.
The transfer functions (for phase and frequency) contain an additional zero at Nyquist.
The PLL locks to any frequency (i.e. it locks to the alias in the first Nyquist zone) and is stable for any numerically valid gain (in units of the sample rate: 7e-5 to 5e-2). It has a single parameter that determines the loop bandwidth. The gains can be changed freely between updates.
All math is naturally wrapping 32 bit integer. Phase and frequency are understood modulo that overflow in the first Nyquist zone. Expressing the IIR equations in other ways (e.g. single (T)-DF-{I,II} biquad/IIR) would break on overflow (i.e. every cycle).
There are no floating point rounding errors. The integer quantization/truncation error is fed back (first order noise shaping).
This PLL clamps phase wraps accumulated during (frequency) lock acquisition.
The phase detector is symmetric (additive): the loop filter has negative gain. The output will compensate the input phase: it will settle to the complement. The output phase increment (the loop filter output, the frequency) is the negative of the input increment.
Fields§
§ba: [Q32<32>; 3]Lead lag coefficients
f0 += b0*y0 + b1*y1 + a1*f1