Crate fls

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Patent pending: DE102021112017A1

§Algorithm description

This application can be understood as a universal phase (frequency) signal processor. It determines the phase (we will drop frequency from now on as in a phase-aware system frequency is merely the difference between successive phases) of an RF input signal and emits an RF output signal with a phase that depends on the input phase. The transfer function between input and output phase is a sequence of various types of filters (analog RC, digital FIR, IIR, unwrapping, scaling, clipping) designed to implement either high-quality phase measurements or a certain constrained and somewhat exotic phase locked loop that is highly applicable to the task of stabilizing the arm length of an optical Michelson interferometer which in turn occurs when stabilizing the effective path length of an optical frequency transmission system.

The sequence of processing steps is as follows. Analyzing it’s application in the context of optical path length stabilization including laser sources, optical modulators, and photodetectors optical is left as an exercise for the user.

§PLL path

  • DDS locks its sysclk (500 MHz) to XO or external ref
  • DDS emits SYNC signal at sysclk/4
  • Prescaler 1/4 (in CPU)
  • Drives CPU timer counter
  • Counter is captured once per batch (based on CPU clock). See stabilizer::hardware::pounder::timestamp.
  • Digital PLL reconstructs SYNC frequency and phase (thus sysclk) w.r.t. batch and sample frequency and phase. This determines the relation of the CPU 8 MHz crystal (thus CPU clock and timers) to the DDS clock (derived from an external reference frequency or internal XCO). See idsp::PLL.

§Signal path

  • RF signal enters Pounder at Pounder IN0
  • Adjustable attenuation demod_att.
  • 30 dB gain block
  • Mixing with DDS at demod_freq
  • RC lowpass and amplification to reject unwanted demodulation products and harmonics
  • IF signal enters Stabilizer and is available at ADC0 for analog monitoring
  • 2x PGIA and AA filter on Stabilizer
  • ADC digitization at 1/1.28 µs interval
  • Data processing in batches of 8 samples
  • Digital mixing with the reconstructed sample phase (PLL path). See idsp::Lockin.
  • Lowpass filtering with a second order (12 dB/octave) IIR lowpass with an additional double zero at Nyquist. Adjustable corner frequency. See idsp::Lowpass
  • Full rate baseband demodulated data (quadrature only) on DAC0
  • Lowpass filtering with a batch-size boxcar FIR filter (zeros at n/4 Nyquist)
  • Computation of signal power and phase. See idsp::ComplexExt.
  • Fractional rescaling (phase_scale) and unwrapping of the phase with 32 bit turn range.
  • Scaling and clamping.
  • Filtering by a second order (biquad) IIR filter (supporting e.g. II, I, P action). See idsp::iir.
  • Clamping, output offset, and anti-windup. See idsp::iir.
  • Feedback onto a frequency offset of the modulation DDS at mod_freq
  • Additional feedback path from the phase before unwrapping onto the modulation DDS phase offset with an adjustable gain pow_gain
  • Adjustable DDS output amplitude and blanking on digital input
  • Adjustable modulation attenuation mod_att
  • Modulation output at Pounder OUT0

§Telemetry

Data is regularly published via MQTT. See Telemetry.

§Streaming

Full-rate ADC and DAC data is available via configurable UDP data streaming. See stream. To view and analyze noise spectra the graphical application stabilizer-stream can be used.

Modules§

app
The RTIC application module
biquad_update 🔒
phase_scale 🔒
validate_att 🔒

Structs§

BiquadRepr
ChannelSettings 🔒
ChannelState
ChannelTelemetry 🔒
Channel Telemetry
CookedTelemetry
Telemetry structure. This structure is published via MQTT at the telemetry_interval configured in Settings. There is no dedicated AA filtering for telemetry data (except for stats), it is just decimated by the telemetry interval. Use streaming for full bandwidth data.
DdsSettings 🔒
Fls
Settings structure for the application. All fields in this structure are available through MQTT and can be configured at runtime.
Settings
Stream 🔒
Stream data format.
Telemetry

Constants§

BATCH_SIZE 🔒
ADC/DAC Samples per batch. The app::process routine is invoked once per batch period and has access to the two (both channels) filled buffers of ADC samples from the previous batch period and to the two to-be-filled buffers of DAC samples that will be emitted in the next batch period.
BATCH_SIZE_LOG2 🔒
DDS_LSB_PER_HZ 🔒
F_DEMOD 🔒
MULT_SHIFT 🔒
PHASE_SCALE_SHIFT 🔒
SAMPLE_TICKS 🔒
ADC and DAC sample rate in timer cycles. One timer cycle at 100 MHz is 10 ns.
SAMPLE_TICKS_LOG2 🔒
Sample and batch period configuration. Note that both SAMPLE_TICKS_LOG2 and BATCH_SIZE_LOG2 are implicitly used in the lockin harmonic computation below. Do not change them without accounting for that.

Type Aliases§

LockinLowpass 🔒