Module stabilizer::hardware::dac

Stabilizer DAC management interface

Design

Stabilizer DACs are connected to the MCU via a simplex, SPI-compatible interface. Each DAC accepts a 16-bit output code.

In order to maximize CPU processing time, the DAC code updates are offloaded to hardware using a timer compare channel, DMA stream, and the DAC SPI interface.

The timer comparison channel is configured to generate a DMA request whenever the comparison occurs. Thus, whenever a comparison happens, a single DAC code can be written to the output. By configuring a DMA stream for a number of successive DAC codes, hardware can regularly update the DAC without requiring the CPU.

In order to ensure alignment between the ADC sample batches and DAC output code batches, a DAC output batch is always exactly 3 batches after the ADC batch that generated it.

The DMA transfer for the DAC output codes utilizes a double-buffer mode to avoid losing any transfer events generated by the timer (for example, when 2 update cycles occur before the DMA transfer completion is handled). In this mode, by the time DMA swaps buffers, there is always a valid buffer in the “next-transfer” double-buffer location for the DMA transfer. Once a transfer completes, software then has exactly one batch duration to fill the next buffer before its transfer begins. If software does not meet this deadline, old data will be repeatedly generated on the output and output will be shifted by one batch.

Multiple Samples to Single DAC Codes

For some applications, it may be desirable to generate a single DAC code from multiple ADC samples. In order to maintain timing characteristics between ADC samples and DAC code outputs, applications are required to generate one DAC code for each ADC sample. To accomodate mapping multiple inputs to a single output, the output code can be repeated a number of times in the output buffer corresponding with the number of input samples that were used to generate it.

Note

There is a very small amount of latency between updating the two DACs due to bus matrix priority. As such, one of the DACs will be updated marginally earlier before the other because the DMA requests are generated simultaneously. This can be avoided by providing a known offset to other DMA requests, which can be completed by setting e.g. DAC0’s comparison to a counter value of 2 and DAC1’s comparison to a counter value of 3. This will have the effect of generating the DAC updates with a known latency of 1 timer tick to each other and prevent the DMAs from racing for the bus. As implemented, the DMA channels utilize natural priority of the DMA channels to arbitrate which transfer occurs first.

Limitations

While double-buffered mode is used for DMA to avoid lost DAC-update events, there is no check for re-use of a previously provided DAC output buffer. It is assumed that the DMA request is served promptly after the transfer completes.

Structs

• Dac0Output
  Represents data associated with DAC.
• Dac1Output
  Represents data associated with DAC.
• DacCode
  Custom type for referencing DAC output codes. The internal integer is the raw code written to the DAC output register.